Semiconductor system

ABSTRACT

A semiconductor system includes a first clock channel and a second clock channel. The first clock channel transmits a first clock signal from a controller to a memory. The second clock channel transmits a second clock signal with a phase difference of 90° from the first clock signal, from the controller to the memory.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) toKorean application number 10-2011-0096135, filed on Sep. 23, 2011, inthe Korean Intellectual Property Office, which is incorporated herein byreference in its entirety as set forth in full.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor system, and moreparticularly, to a semiconductor system including a controller and amemory.

2. Related Art

A controller and a memory in a semiconductor system communicate witheach other through a plurality of channels. The channels include acommand channel for transmitting a command signal, a clock channel fortransmitting a clock signal, a data channel for transmitting a datasignal, and so forth. The controller transmits a clock signal to thememory and transmits a command signal and a data signal insynchronization with the clock signal. The memory receives the clocksignal through the clock channel, and receives the command signal andthe data through the command channel and the data channel, respectively,in synchronization with the clock signal. Accordingly, the controllerand the memory can communicate with each other based on the clocksignal.

FIG. 1 is an exemplary timing diagram showing clock signals transmittedfrom a controller to a memory through channels and internal clocksignals generated within the memory. The controller transmits a firstclock signal HCLK and a second clock signal WCLK to the memory. Thesecond clock signal WCLK is a clock that may be used for datainput/output operations, and the first clock HCLK is a clock signal thatmay be used for operations other than the data input/output operations.The memory receives the first and second clock signals HCLK and WCLK andgenerates first and second internal clock signals CLK0 and CLK90. Thefirst and second clock signals CLK0 and CLK90 are generated, forexample, to allow the memory to perform a double data rate (DDR)operation. The phase difference between the first and second clocksignals CLK0 and CLK90 is 90°, and data can be inputted and outputted insynchronization with the rising edge and the falling edge of the secondclock signal WCLK.

The controller generates and outputs the second clock signal WCLK, whichhas the same phase as the first clock signal HCLK and twice thefrequency of the first clock signal HCLK, for high speed datacommunication with the memory. A clock generation unit is provided inthe memory to receive the first and second clock signals HCLK and WCLKand to generate the first and second internal clock signals CLK0 andCLK90. The clock generation unit generates two clock signals, one signalwith a 90° phase shift, because the memory does not operate internallywith a clock at the same frequency of the second clock signal WCLK.

The memory provides feedback information to the controller regardingwhether the first and second clock signals HCLK and WCLK have acorresponding phase. When the phases of the first and second clocksignals HCLK and WCLK do not correspond to each other, a trainingoperation is performed to correct the first and second clock signalsHCLK and WCLK so that the first and second clock signals HCLK and WCLKcorrespond in phase. Therefore, the controller and the memory may havecircuits that perform the training operation.

FIGS. 2 a and 2 b are timing diagrams respectively showing situationswhere first and second internal clock signals are normally generated andwhere the first and second internal clock signals are generated witherroneous timing, with respect to a power-down mode exit time. Thememory may operate in a power-down mode to reduce power consumption, anddata communication is not performed in the power-down mode. The memoryoperates in power-down mode when the power down signal PWRDN is at ahigh level. Accordingly, the memory may not receive the second clocksignal WCLK in the power-down mode. When the memory no longer operatesin the power-down mode, the memory may receive the first and secondclock signals HCLK and WCLK and generate the first and second internalclock signals CLK0 and CLK90. Referring to FIG. 2A, the memory generatesthe first internal clock signal CLK0 at the rising edge of the secondclock WCLK. When the power-down signal PWRDN changes to a low level(Power down mode exit) during a low level duration of the first clocksignal HCLK, the first internal clock signal CLK0 may be normallygenerated at the rising edges of the first clock signal HCLK and thesecond clock signal WCLK.

Conversely, referring to FIG. 2B, when the power down exit happensduring a high level duration of the first clock signal HCLK, the firstinternal clock signal CLK0 is generated at the falling edge of the firstclock signal HCLK and the rising edge of the second clock signal WCLK.In this situation, the memory creates erroneous timing. In response tothe erroneous timing, the controller may transmit a command to thememory to invert the phases of the first internal clock signal CLK0 andthe second internal clock signal CLK90 to generate the first internalclock signal CLK0 at the rising edges of the first clock signal HCLK andthe second clock signal WCLK.

SUMMARY

A semiconductor system including channels for transmitting multi-phaseclocks is described in the following disclosure.

In an exemplary embodiment of the present invention, a semiconductorsystem includes: a first clock channel configured to transmit a firstclock signal from a controller to a memory; and a second clock channelconfigured to transmit a second clock signal with a phase difference of90° from the first clock signal, from the controller to the memory.

In another exemplary embodiment of the present invention, asemiconductor system includes: a first clock channel configured totransmit a first clock signal from a controller to a memory; a secondclock channel configured to transmit a second clock signal with the samefrequency as the first clock signal, from the controller to the memory;and a third clock channel configured to transmit a third clock signalwith the same frequency as the second clock signal and a different phasefrom the second clock signal, from the controller to the memory.

In another exemplary embodiment of the present invention, asemiconductor system includes: a controller configured to output a firstclock signal and a second clock signal with a phase difference of 90°from the first clock signal, in a normal mode; and a memory configuredto operate in response to the first and second clock signals.

In another exemplary embodiment of the present invention, asemiconductor system includes: a controller configured to output a firstclock signal, a second clock signal with the same frequency as the firstclock signal, and a third clock signal with the same frequency as thesecond clock signal and a different phase from the second clock signal,in a normal mode; and a memory configured to operate in response to thefirst through third clock signals.

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with theattached drawings, in which:

FIG. 1 is a timing diagram exemplarily illustrating clock signalstransmitted from a controller to a memory through channels and internalclock signals generated in the memory;

FIGS. 2 a and 2 b are timing diagrams respectively illustrating thecases where first and second internal clock signals are normallygenerated and where first and second internal clock signals aregenerated at erroneous timing, with respect to a power-down mode exittime;

FIG. 3 is of a schematic block diagram of a semiconductor system inaccordance with an exemplary embodiment of the present invention and atiming diagram illustrating clock signals transmitted through channels;and

FIG. 4 is of a schematic block diagram of a semiconductor system inaccordance with another exemplary embodiment of the present inventionand a timing diagram illustrating clock signals transmitted throughchannels.

DETAILED DESCRIPTION

In the following disclosure, a semiconductor system according to thepresent invention will be described below with reference to theaccompanying drawings through exemplary embodiments.

Referring to FIG. 3, the semiconductor system includes a controller 100and a memory 200. The controller 100 and the memory 200 communicate witheach other through a plurality of channels. The plurality of channelsmay include a command channel, a clock channel, a data channel, and soforth. The controller 100 and the memory 200 may communicate with eachother by transmitting signals through the plurality of channels. In FIG.3, the clock channel is shown. The clock channel includes first andsecond clock channels 10 and 20. The memory 200 may receive the clocksignals output from the controller 100 through the clock channels 10 and20 and may operate in synchronization with the controller 100.

The controller 100 outputs a first clock signal HCLK0 through the firstclock channel 10 to the memory 200. The controller 100 outputs a secondclock signal HCLK90 to the memory 200 through the second clock channel20.

In an embodiment of the present invention, the first clock signal HCLK0and the second clock signal HCLK90 have the same frequency. The secondclock signal HCLK90 has a phase difference of 90° from the first clocksignal HCLK0. The controller 100 includes a phase-locked loop (PLL)circuit 110. The first and second clock signals HCLK0 and HCLK90 aregenerated by the phase-locked loop circuit 110. The phase-locked loopcircuit 110 may be capable of generating a multi-phase clock. Sincecontroller 100 has the phase-locked loop circuit 110, a separate clockgeneration circuit is not included in addition to the phase-locked loopcircuit 110 in the controller 100 or the memory 200 to generate thefirst clock signal HCLK0 and the second clock signal HCLK90.

The memory 200 may receive the first clock signal HCLK0 and the secondclock signal HCLK90 and may generate four internal clock signals CLK0,CLK90, CLK180 and CLK270. The memory may use a differential clock signalHCLK180 of the first clock signal HCLK0 and a differential clock signalHCLK270 of the second clock signal HCLK90 to generate the four internalclock signals CLK0, CLK90, CLK180 and CLK270. The internal clock signalsCLK90, CLK180, and CLK270 each sequentially have an additional 90° ofphase difference from CLK0. The internal clock signals CLK0, CLK90,CLK180 and CLK270 are used when the memory 200 receives data from thecontroller 100 and outputs data to the controller 100.

The memory 200 may enter a power-down mode or exit the power-down modeto enter a normal mode under the control of the controller 100. Thepower-down mode may be referred to as a low power consumption mode or astandby mode, and may be a mode where power consumption by the memory200 is reduced. The normal mode may be all modes or operating statesexcluding the power-down mode. In the power-down mode, the memory 200does not perform data communication with the controller 100. When thememory 200 exits the power-down mode to enter the normal mode, thememory 200 may be quickly reset to prepare for communication with thecontroller 100. In the power-down mode, the controller 100 may outputthe first clock signal HCLK0 but may not output the second clock signalHCLK90. Accordingly, since the controller 100 outputs only the firstclock signal HCLK0, power consumption may be reduced because thecontroller does not toggle the second clock signal HCLK90.

In the normal mode, the controller 100 outputs both the first and secondclock signals HCLK0 and HCLK90, and the memory 200 receives both thefirst and second clock signals HCLK0 and HCLK90. The memory 200 mayimmediately generate the internal clock signals CLK0, CLK90, CLK180 andCLK270 for data communication by receiving the first and second clocksignals HCLK0 and HCLK90. The internal clock signals CLK180 and CLK270may be generated through circuits that invert the internal clock signalsCLK0 and CLK90 or may be generated from clock signals that aretransmitted from the controller 100 to the memory 200 through separateclock channels.

In an embodiment of the present invention, the controller 100 mayfurther output third and fourth clock signals HCLK180 and HCLK270. Also,the semiconductor system may further include third and fourth clockchannels (not shown) for transmitting the third and fourth clock signalsHCLK180 and HCLK270 to the memory 200. The third clock signal HCLK180has a phase difference of 180° from the first clock signal HCLK0, andthe fourth clock signal HCLK270 has a phase difference of 270° from thefirst clock signal HCLK0. The four internal clock signals CLK0, CLK90,CLK180 and CLK270 may be immediately generated by receiving the fourclock signals HCLK0, HCLK90, HCLK180 and HCLK270 through the four clockchannels. In other words, a clock generation unit, to generate theinternal clocks CLK0, CLK90, CLK180 and CLK270 for data input/outputoperations, is not included in the memory 200. Moreover, when the memory200 switches from power-down mode to normal mode, the internal clocksCLK0, CLK90, CLK180 and CLK270 may be immediately generated by receivingthe first through fourth clocks HCLK0, HCLK90, HCLK180 and HCLK270.Therefore, when the memory 200 switches from power-down mode to normalmode, a quick reset may be performed.

Referring to FIG. 4, the semiconductor system includes a controller 300,a memory 400, first, second, and third clock channels 50, 60 and 70. Thecontroller 300 generates and outputs first, second, and third clocksignals HCLK0, WCLK0 and WCLK90. The first, second, and third clockchannels 50, 60 and 70 respectively transmit the first, second, andthird clock signals HCLK0, WCLK0 and WCLK90, and the memory 400 receivesthe first, second, and third clock signals HCLK0, WCLK0 and WCLK90.

In an embodiment of the present invention, the second clock signal WCLK0has the same frequency as the first clock signal HCLK0. The third clocksignal WCLK90 has the same frequency as the second clock signal WCLK0but has a different phase from the second clock signal WCLK0. The thirdclock signal WCLK90 may have a phase difference of 90° from the secondclock signal WCLK0.

The second and third clock signals WCLK0 and WCLK90 are clock signalsused when the memory 400 receives data from the controller 300 oroutputs data to the controller 300. The first clock signal HCLK0 is aclock signal used for operations other than the data input/outputoperations of the memory 400, and, for example, may be a clock signalused to process signals, such as a command signal and an address signalreceived from the controller 300. For the data input/output operationsof the memory 400, clock signals other than the first clock signal HCLK0may be used to communicate with the controller 300. Moreover, in thememory 400, a circuit block for data input/output operations and acircuit block for the other operations are separated from each other interms of position and structure. The separate clock signals for datainput/output operations and the clock signal for processing the commandand address signals facilitates communication between the controller 300and the memory 400.

The first, second, and third clock signals HCLK0, WCLK0 and WCLK90 maybe generated from a phase-locked loop circuit 310 that is included inthe controller 300. The memory 400 may receive the second clock signalWCLK0 and the third clock signal WCLK90 and generate four internal clocksignals CLK0, CLK90, CLK180 and CLK270. The memory 400 may use adifferential clock signal WCLK180 of the second clock signal WCLK0 and adifferential clock signal WCLK270 of the third clock signal WCLK90 togenerate the four internal clock signals CLK0, CLK90, CLK180 and CLK270.The internal clock signals CLK90, CLK180, and CLK270 each sequentiallyhave an additional 90° of phase difference from CLK0. These internalclock signals CLK0, CLK90, CLK180 and CLK270 are used when the memory400 receives data from the controller 300 and outputs data to thecontroller 300.

During a power-down mode, the controller 300 outputs the first clocksignal HCLK0 but does not output the second and third clock signalsWCLK0 and WCLK90, and the memory 400 receives the first clock signalHCLK0 and does not receive the second and third clock signals WCLK0 andWCLK90.

If the semiconductor system switches from power-down mode to normalmode, the memory 400 receives the first, second, and third clock signalsHCLK0, WCLK0 and WCLK90 from the controller 300. The memory 400 receivesthe second and third clock signals WCLK0 and WCLK90 and generates theinternal clock signals CLK0, CLK90, CLK180 and CLK270. The memory 400may immediately generate the internal clock signals CLK0, CLK90, CLK180and CLK270 based on the second and third clock signals WCLK0 and WCLK90.The internal clock signals CLK180 and CLK270 may be generated throughcircuits for inverting the internal clock signals CLK0 and CLK90 in thememory 400 or may be generated from clock signals which are transmittedfrom the controller 300 to the memory 400 through separate clockchannels.

The semiconductor system may further include a fourth clock channel fortransmitting a fourth clock signal HCLK180 with a phase difference of180° from the first clock signal HCLK0. The semiconductor system mayfurther include a fifth clock channel for transmitting a fifth clocksignal WCLK180 with a phase difference of 180° from the second clocksignal WCLK0. The semiconductor system may further include a sixth clockchannel for transmitting a sixth clock signal WCLK270 with a phasedifference of 180° from the third clock signal WCLK90.

Since the controller 300 may generate the first through sixth clocksignals HCLK0, WCLK0, WCLK90, HCLK180, WCLK180 and WCLK270 using thephase-locked loop circuit 310, the controller 300 does not have separateclock generation circuits. Since the memory 400 may generate theinternal clock signals CLK0, CLK90, CLK180 and CLK270 based on the firstthrough sixth clock signals HCLK0, WCLK0, WCLK90, HCLK180, WCLK180 andWCLK270 immediately when switching from power-down mode to normal mode,the memory 400 does not need a separate clock generation circuit.Furthermore, the semiconductor system does not need a training operationbetween the controller 300 and the memory 400 and a circuit for thetraining operation.

As is apparent from the above description, since additional circuits fortraining operations are not included, a circuit area may be madeavailable. Also, when switching from power-down mode to normal mode, thememory is capable of performing a quick reset. Further, powerconsumption is reduced since clock signals that are transmitted throughthe channels have a constant frequency.

While certain embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare by way of example only. Accordingly, the semiconductor systemdescribed herein should not be limited based on the describedembodiments. Rather, the semiconductor system described herein shouldonly be limited in light of the claims that follow when taken inconjunction with the above description and accompanying drawings.

What is claimed is:
 1. A semiconductor system comprising: a first clockchannel configured to transmit a first clock signal from a controller toa memory; and a second clock channel configured to transmit a secondclock signal with a phase difference of 90 degrees from the first clocksignal, from the controller to the memory.
 2. The semiconductor systemaccording to claim 1, wherein the second clock signal is generated by aphase-locked loop circuit that is included in the controller.
 3. Thesemiconductor system according to claim 1, wherein the first and secondclock signals have the same frequency.
 4. The semiconductor systemaccording to claim 1, further comprising: a third clock channelconfigured to transmit a third clock signal with a phase difference of180 degrees from the first clock signal, from the controller to thememory.
 5. The semiconductor system according to claim 4, furthercomprising: a fourth clock channel configured to transmit a fourth clocksignal with a phase difference of 180 degrees from the second clocksignal, from the controller to the memory.
 6. A semiconductor systemcomprising: a first clock channel configured to transmit a first clocksignal from a controller to a memory; a second clock channel configuredto transmit a second clock signal with the same frequency as the firstclock signal, from the controller to the memory; and a third clockchannel configured to transmit a third clock signal with the samefrequency as the second clock signal and a different phase from thesecond clock signal, from the controller to the memory.
 7. Thesemiconductor system according to claim 6, wherein the first and secondclock signals have the same phase.
 8. The semiconductor system accordingto claim 6, wherein the third clock signal has a phase difference of 90degrees from the second clock signal.
 9. The semiconductor systemaccording to claim 6, wherein the first through third clock signals aregenerated by a phase-locked loop circuit that is included in thecontroller.
 10. The semiconductor system according to claim 6, furthercomprising: a fourth clock channel configured to transmit a fourth clocksignal with a phase difference of 180 degrees from the first clocksignal, from the controller to the memory.
 11. The semiconductor systemaccording to claim 6, further comprising: a fifth clock channelconfigured to transmit a fifth clock signal with a phase difference of180 degrees from the second clock signal, from the controller to thememory.
 12. The semiconductor system according to claim 11, furthercomprising: a sixth clock channel configured to transmit a sixth clocksignal with a phase difference of 180 degrees from the third clocksignal, from the controller to the memory.
 13. The semiconductor systemaccording to claim 6, wherein the memory uses the second and third clocksignals for data input/output operations and uses the first clock signalfor operations other than the data input/output operations.
 14. Asemiconductor system comprising: a controller configured to output afirst clock signal and a second clock signal with a phase difference of90 degrees from the first clock signal, in a normal mode; and a memoryconfigured to operate in response to the first and second clock signals.15. The semiconductor system according to claim 14, wherein thecontroller includes a phase-locked loop circuit which generates thefirst and second clock signals.
 16. The semiconductor system accordingto claim 14, wherein the controller outputs the first clock signal anddoes not output the second clock signal in a power-down mode.
 17. Thesemiconductor system according to claim 14, wherein the controllerfurther outputs a third clock signal with a phase difference of 180degrees from the first clock signal and a fourth clock signal with aphase difference of 180 degrees from the second clock signal.
 18. Asemiconductor system comprising: a controller configured to output afirst clock signal, a second clock signal with the same frequency as thefirst clock signal, and a third clock signal with the same frequency asthe second clock signal and a different phase from the second clocksignal, in a normal mode; and a memory configured to operate in responseto the first through third clock signals.
 19. The semiconductor systemaccording to claim 18, wherein the first clock signal and the secondclock signal have the same phase.
 20. The semiconductor system accordingto claim 18, wherein the third clock signal has a phase difference of 90degrees from the second clock signal.
 21. The semiconductor systemaccording to claim 18, wherein the controller includes a phase-lockedloop circuit that generates the first through third clock signals. 22.The semiconductor system according to claim 18, wherein the controllerconfigured to output the first clock signal and does not output thesecond and third clock signals in a power-down mode.
 23. Thesemiconductor system according to claim 18, wherein the controllerfurther outputs a fourth clock signal with a phase difference of 180degrees from the first clock signal, a fifth clock signal with a phasedifference of 180 degrees from the second clock signal, and a sixthclock signal with a phase difference of 180 degrees from the third clocksignal.
 24. The semiconductor system according to claim 18, wherein thememory configured to perform data input/output operations in response tothe second and third clock signals, and uses the first clock signal whenperforming operations excluding the data input/output operations. 25.The semiconductor system according to claim 18, wherein the memoryconfigured to receive the first through third clock signals andgenerates a first internal clock signal, a second internal clock signal,a third internal clock signal, and a fourth internal clock signal. 26.The semiconductor system according to claim 19, wherein the firstthrough fourth internal clock signals are immediately generated byreceiving the first through third clock signals from the controller.